LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations

First, this paper considers the number of LUTs to implement logic functions based on MUX-based realization and cascade realization. This is useful to quickly estimate the number of LUTs to implement the functions on a FPGA. Second, this paper shows an algorithm to realize logic functions by 6-LUTs using cascade and MUX-based realizations. It often produces smaller circuits than previous methods when the number of the input variables is smaller than 16.